This invention relates to a semiconductor device and, more particularly, to a semiconductor device in which a reduction of a parasitic capacitance between a substrate and a conductive layer utilized for wiring is needed in order to improve the operation speed.
FIG. 1 illustrates a structure of a general MOS (Metal Oxide Semiconductor) transistor device according to the prior art. FIG. 1(a) is a sectional view of an N channel transistor device and FIG. 1(b) is a sectional view of a CMOS (Complimentary Metal Oxide Semiconductor) transistor device. In both the devices, device regions X and isolation regions Y are defined on a P-type substrate 1. In the device region X of the device shown in FIG. 1(a), an N channel MOS transistor is constructed which comprises an N.sup.+ -buried layer 2 (a layer implanted with an N.sup.+ -type impurity), a gate oxide 3, and a gate electrode 4. On the other hand, in the device region X of the device shown in FIG. 1(b), a P channel MOS transistor is constructed in an N-well 5 as well as an N channel MOS transistor. The P channel MOS transistor comprises a P.sup.+ -buried layer 6, a gate oxide 3, and a gate electrode 4. In order to isolate these device regions X, field oxides 7 are constructed in the isolation regions Y. The transistors and the field oxides 7 are coated with insulative protection layers 8. After forming contact windows, interconnection layers 9 are formed through protection layers 8. Then conductive layers 10 are formed on the protection layers 8 in the isolation regions Y so as to wire the transistors.
In the operation mode of the above described MOS transistors, it is considered that there are three different types of capacitance elements which behave as loads in a circuit, that is, (i) a junction capacitance between the substrate 1 and the N.sup.+ -buried layer 2 which corresponds to a source or a drain; (ii) a capacitance between the gate 4 and the substrate 1; and (iii) a capacitance between the substrate 1 and the conductive layer 10. When the size of a transistor becomes smaller due to an integration of an LSI, the above mentioned capacitances (i) and (ii) are reduced. However, the capacitance (iii) tends to increase because the integration of the LSI lengthens the conductive layer and increases the thickness of the field oxides. Since the capacitance behaves as a load in a circuit, an operation speed of the circuit becomes low with increasing capacitance. Therefore the increase in the capacitance described above causes a serious problem in the LSI.